Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - Verilog fir filter

Search list

[Other resource] fir2

Description: Verilog 编写的fir滤波器，可以实现fir滤波器的功能-Verilog prepared by the fir filter can achieve fir filter function
Platform: | Size: 12638 | Author: 宋南 | Hits:

[VHDL-FPGA-Verilog] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112640 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[Communication-Mobile] DDC

Description: 个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR-DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
Platform: | Size: 2048 | Author: yeong | Hits:

[VHDL-FPGA-Verilog] base_fir

Description: 使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
Platform: | Size: 21504 | Author: xiaoLEE | Hits:

[DSP program] dspddc_R12p1

Description: 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
Platform: | Size: 17408 | Author: 郑程 | Hits:

[VHDL-FPGA-Verilog] 11orderFIR

Description: 11阶FIR数字滤波器，Verilog版本，数字下变频，适合初学-11-order FIR digital filter, Verilog version of the digital down conversion, suitable for beginners
Platform: | Size: 1024 | Author: 王刚 | Hits:

[Communication-Mobile] firVerilog

Description: 用verilog语言编写的一个FIR滤波器的程序-Verilog language with a FIR filter process
Platform: | Size: 4096 | Author: 夏宝平 | Hits:

[VHDL-FPGA-Verilog] FIR_chanbing

Description: 串并结构的FIR滤波器,Verilog语言编写，希望对大家有帮助-String and the structure of FIR filter, Verilog language, we want to help
Platform: | Size: 13312 | Author: | Hits:

[VHDL-FPGA-Verilog] fir_filter

Description: 一种fir滤波器的verilog程序，非常实用-fir filter very good write by verilog
Platform: | Size: 1024 | Author: ningbo | Hits:

[VHDL-FPGA-Verilog] ourdev_573514

Description: 高通滤波器的verilog实现，对初学者设计FIR有好处，分布式算法-Verilog implementation of high-pass filter, FIR design is good for beginners, distributed algorithm
Platform: | Size: 306176 | Author: 吴锦干 | Hits:

[VHDL-FPGA-Verilog] LPF

Description: 数字低通FIR滤波器Verilog实现代码-Verilog digital FIR filter implementation code
Platform: | Size: 4096 | Author: 程超 | Hits:

[VHDL-FPGA-Verilog] firlms

Description: 基于FPGA的自适应FIR滤波器的verilog设计与实现-Adaptive FIR Filter Based FPGA Design and Implementation of verilog
Platform: | Size: 1024 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] robust_fir_latest.tar

Description: RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).-RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).
Platform: | Size: 6144 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] fir_filter_generator

Description: FIR有限冲击响应滤波器verilog代码和测试-FIR finite FIR filter verilog code and test
Platform: | Size: 1845248 | Author: 李雪利 | Hits:

[VHDL-FPGA-Verilog] firfilt

Description: FIR滤波器verilog源代码，经过fpga验证可以被综合。-FIR filter verilog source code, fpga verification can be integrated.
Platform: | Size: 5120 | Author: mmmm1111111111 | Hits:

[Graph program] filter_dds_10.29_7.2

Description: 一个经过处理的FIR filter, verilog HDL实现在FPGA上-One new design of digital FIR filter , which can be implemented in FPGA kit
Platform: | Size: 1033216 | Author: chen | Hits:

[Windows Develop] TverilogFIRh

Description: 基于verilog的FIR滤波器程序设计（调试过的的）-verilog ， -Verilog program of FIR filter design (debug)-Verilog,
Platform: | Size: 645120 | Author: 表现 | Hits:

[VHDL-FPGA-Verilog] HalfbandDec

Description: 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
Platform: | Size: 1024 | Author: 小梦 | Hits:

[Other] FIR_lowpass

Description: FIR 滤波器 verilog 语言编写 很实用-FIR filter design
Platform: | Size: 1024 | Author: 小关 | Hits:
« 1 2 3 4 5 67 8 »

CodeBus www.codebus.net